A new approach for pipeline time-to-digital converters (TDCs) is introduced in this paper. The analog interpolation and voltage amplification methods for digitalizing the time intervals between the rising edges of two input signals are employed in the recommended converter. It consists of four 2.5b/stage time-to-digital converters and three voltage amplifiers (VAs) and will be a 9-bit pipeline TDC. Besides, a new VA is suggested in this paper. The delay cells such as delay line TDCs and vernier delay line TDCs (VDL–TDCs) are not used in this converter. Moreover, a triple-slope conversion is achieved by performing of the interpolation. Lots of advantages can be mentioned for the proposed converter such as; lower complexity, lower temperature sensitivity, power supply and process (PVT) variations, and higher accuracy in comparison with the time-to-digital converters which have been proposed previously. Furthermore, the differential non linearity (DNL) and the integral non linearity (INL) errors are decreased while the dynamic range, the time resolution, and the linear range of the TDC are developed significantly. The simulation results for INL and DNL in the proposed TDC are 0.83 LSB and 0.92 LSB, correspondingly. In addition, the time resolution is improved to 0.234 ps. To verify the validity of theoretical analysis, designing and simulation of the TDC is done in TSMC 45 nm CMOS technology. The comparison between the theoretical analysis and simulation results approves the superiorities and characteristics of the proposed TDC.
